Intel recently announced it’s awarded the second phase of the Navy’s SHIP program. How is Intel part of a “ship” program? For that, we need to stay on top of the acronyms.
SHIP, when spelled out, is State-of-the-art Heterogeneous Integration Prototype.
Intel’s press release points out that the SHIP program will allow the U.S. military to access Intel’s advanced semiconductor packaging capabilities in Arizona and Oregon and take advantage of heterogeneous integration/advanced packaging technologies Intel has developed by using chiplets. The program’s focus is more on the warrior than the consumer, with a goal to enable rapid prototyping.
Before we think about the Intel announcement, let’s look at the history of the programs that led to SHIP.
There have been a few milestones on the way to the SHIP program. At some point, influencers inside the U.S. Department of Defense (DoD) recognized that the conventional procurement programs lacked the agility for the military to remain technologically superior.
After realizing that change was necessary, DoD instituted the Other Transaction Authority (OTA). There are several goals written into the legislation that launched the OTA methodology, but it is commonly summed up as a new DoD approach that eliminates red tape to fast-track prototyping contracts with suppliers.
Building upon the OTA, the cleverly titled “CHIPS (Common Heterogeneous Integration and IP Reuse Strategies)” program was created. (The military must have entire units devoted to acronyms.)
The Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies recognized that the SoC trends of the broader semiconductor industry had created impediments to the military. The vision of the program was to look at reusable IP blocks as chiplets rather than bits and pieces to be stitched together for a new SoC design. A great overview of the details of the legislation and what it means can be found here.
Is DoD moving toward a commercial, off-the-shelf (COTS) approach to military procurement? That is part of the strategy, but there is more.
CHIPS offered a new direction, but it was only a concept. The Defense Advanced Research Projects Agency (DARPA) website bills it as, “The vision of…an ecosystem of discrete modular, reusable IP blocks, which can be assembled into a system using existing and emerging integration technologies.” As we know, dreams and visions don’t get far without engineers and technologists to execute them.
Recommended
- Taking a Closer Look at Intel’s Process Roadmap
- Heterogeneous integration enables advanced IC packaging
- Intel’s Path to 10nm: Past, Present, and Future
- Intel’s Path to 10nm: Past, Present, and Future – Part 2
The SHIP
I have not yet uncovered the Naval Department of Poetry (NDOP?), but a trend is emerging with the rapid prototyping initiative. Building on DARPA’s CHIPS, the Naval Surface Warfare Center, Crane Division (NSWC Crane) awarded multiple contracts in 2019 to ensure “access to secure advanced assembly, packaging and test of digital and RF microelectronics, which is a DoD priority and critical to the department’s microelectronics strategy.” This is where we get back onto the SHIP (state-of-the-art heterogeneous integration prototype).
It isn’t a critical part of this thread, but I should give credit to another great acronym. The particular OTA used by NSWC Crane for the SHIP program was S2MARTS or Strategic & Spectrum Missions Advanced Resilient Trusted Systems.
One may speculate about the next in the series of rhyming acronyms, but for today, we just have SHIP. The original awardees to the SHIPS program were GE Research, Intel Federal, LLC., Keysight Technologies, Northrop Grumman Aerospace Systems, Qorvo, and Xilinx. According to Brook Pyne, director of the S2MARTS OTA, the SHIP program took 90 days rather than about two years for a typical pre-OTA era program of similar scope.
The theme is speed. The procurement system is built for it. The SHIP partners were chosen to accelerate the design cycle. Intel’s acquired FPGA prowess (Altera) is the key enabler of the rapid prototyping. The FPGA is not technology that will compete in high volumes or for cost-sensitive applications, but it is by far the fastest way to get hardware functionality into the field. The SHIP program also includes the other large FPGA supplier. Xilinx is dominating the news for an entirely different reason.
The hardware FPGA short-circuits the development cycle of an ASIC. An FPGA will also run algorithms on the data from the peripheral chiplets much faster than code running on a CPU. Of course, Intel knows a thing or two about the CPU as well. Intel offers the processing in multiple flavors to run the latest military tech and get it into the most advanced system-level packaging available.
Intel’s advanced packaging with Foveros die stacking, embedded multi-die interconnect bridge (EMIB), and combinations of the two provide the design flexibility and speed of integration specified by the SHIP program. Intel CPUs open up another avenue for the military rapid prototyping program, but the combination of Intel FPGA products and advanced heterogenous system packaging technology are what makes them the perfect fit for the SHIP rapid prototyping concept.
The post How Is Intel Part of a “SHIP” Program? appeared first on EE Times Asia.
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